Electronics have become part of almost every aspect of modern life, from television sets to toasters. As technology progresses, electronic circuits become increasingly complex. Designing a circuit with hundreds or even thousands of individual electronic components has become a great challenge for circuit designers. The challenge becomes even greater when many iterations of prototypes are required to test out the circuits and prove their viability. As the number of components multiply, building the actual circuit and modifying it becomes an expensive and time consuming proposition.
To overcome the problems associated with working with real components, circuit designers turned to computers to aid them with their designs. By using a computer, designers could create “virtual” circuits. This enabled designers to create, modify and test circuits without actually building the circuit with real components. Hardware Description Languages (HDL) were developed to aid designers in creating the virtual circuits. HDL programs allow designers to choose from a standardized set of instructions while designing their circuits on computers. Many different HDL programs have been written, each with varying capabilities. Among these HDL programs is Verilog HDL which is widely used and is considered an industry standard among circuit designers.
Verilog HDL uses the computer to simulate complex circuit designs with various inputs and outputs. It uses “modules” or lines of code representing a desired function as building blocks to create the simulation. The designer builds simulated circuitry by simply selecting and connecting the desired modules. Individual “nodes” or electrical connection points of the circuit can be analyzed while changing input variables to the circuit. The designer can even initialize nodes of the circuitry to various logic values before the simulation is started. Currently, however, this initial node parameter is not stabilized and will “float” or change to an unknown logic value during the simulation run. The designer has no way of knowing when or if the initial condition of the node has changed. If this is crucial to the design, it presents a serious, time consuming issue to surmount.
One method of overcoming this problem is to write a separate simulation program and use Verilog's Programming Language Interface (PLI) to export the desired node value to the separate simulation program. However, this method requires that a specific co-simulation program be written by a programmer for each Verilog simulation. This is both costly and time consuming and slows down the design cycle. Accordingly, what is needed is a simulation initialization and monitoring solution that is both quick and cost effective to use in circuit design, especially when using Verilog HDL.